<ARM>
=
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered #define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask |
=외부 DISABLE
*AT91C_PIOA_IDR = 1<<INT_PIN; // 인터럽트 핀 비 활성화
*AT91C_AIC_IDCR = 1 << AT91C_ID_PIOA; // 인터럽트 핀 컴맨드 비 활성화 -ref) p175
=외부 ENABLE
: 외부 -> PIOA ENABLE(15번핀) -> AIC ENABLE (장치:PIOA) ( 외부 ==> 인터럽트 핸들러 )
: 부산 -> 문(성문) 통과 -> 남대문 통과 ( 부산 ==> 서울 )
*AT91C_PIOA_IER = 1 << INT_PIN; //PIOA 인터럽트 핀 인터럽트 활성화
*AT91C_AIC_IECR = 1 << AT91C_ID_PIOA; //AIC 인터럽트 핀 인터럽트 활성화
=핸들러
=
<HEADER>
// ========== Register definition for AIC peripheral ========== #define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register #define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register #define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register #define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) #define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register #define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register #define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register #define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register #define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register #define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register #define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register #define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register #define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register #define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register |
// ========== Register definition for PMC peripheral ========== #define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register #define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register #define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register #define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register #define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register #define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register #define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register #define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register #define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register #define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register #define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register |
<AIC.H>
#ifndef __AIC_H__ #define __AIC_H__ #include <AT91SAM7S256.h> #include "lcd.h"
#define INT_PIN 15//AT91C_PIO_PA15 void AIC_Init(void); #endif //__AIC_H__ |
<AIC.C>
#include "aic.h"
void HANDLER(void) { volatile unsigned int uiIsr; volatile unsigned int uiCnt;
// 인터럽트 핀 정보 저장 uiIsr = *AT91C_PIOA_ISR; if(0 != (uiIsr & ( 1 << INT_PIN))) // 인터럽트 핀 검색 { //할 일 LCD_Print("Hdlr()"); }
for(uiCnt = 0; 100000 > uiCnt ;++uiCnt); // 지연 - 채터링 심함 (인터럽트가 엄청 많이 호출 됨 ) uiIsr = *AT91C_PIOA_ISR; // ISR 레지스터 클리어 *AT91C_AIC_EOICR = 0; // End code return; }
void AIC_Init(void) { LCD_Init(); *AT91C_PMC_PCER = 1 << AT91C_ID_PIOA; // 전원 공급 (PIOA) - 실제로는 필요 X - ref) p34 *AT91C_PIOA_PER = 1 << INT_PIN; // 핀 활성화 *AT91C_PIOA_ODR = 1 << INT_PIN; // 핀 출력 비활성화 *AT91C_PIOA_IDR = 1<<INT_PIN; // 인터럽트 핀 비 활성화 *AT91C_PIOA_IFER = 1<<INT_PIN; // PIOA 입력 필터 활성화 -ref) p248 *AT91C_AIC_IDCR = 1 << AT91C_ID_PIOA; // 인터럽트 핀 컴맨드 비 활성화 -ref) p175 *AT91C_AIC_ICCR = 1 << AT91C_ID_PIOA; // 커맨드 레지스터 클리어 *AT91C_AIC_ISCR = 1 << AT91C_ID_PIOA; // 커맨드 레지스터 셋 AT91C_AIC_SVR[AT91C_ID_PIOA] = (unsigned int)HANDLER;// 핸들러 등록 // 동작모드 및 우선순위 결정 -ref) p176 AT91C_AIC_SMR[AT91C_ID_PIOA] = AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST; *AT91C_PIOA_IER = 1 << INT_PIN; // PIOA 인터럽트 핀 인터럽트 활성화 -ref) p256 *AT91C_AIC_IECR = 1 << AT91C_ID_PIOA; // AIC 인터럽트 핀 인터럽트 활성화 -ref) p180 return; }
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